Leakage current may be a small current leaking from a device in its off state, caused by semiconductor characteristics of the device. For example, high leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of complementary metal-oxide-semiconductor (CMOS) circuits in the device as the threshold voltage, channel length, and gate oxide thickness of transistors making up the CMOS circuits are continually being reduced due to ongoing efforts to scale down the device.
There may be three major sources of leakage in a device, namely subthreshold leakage, gate leakage, and reverse bias junction leakage. The subthreshold leakage may be caused by current flowing from the drain to the source of a transistor operating in a weak inversion region. The gate leakage may be caused by current flowing from the gate through the oxide to the substrate of the transistor due to the gate oxide tunneling and hot carrier injection. The reverse bias junction leakage may be caused by current flowing from the source or drain to the substrate of the transistor through the reverse-biased diodes. With scaling down of the transistor, each of the leakage sources may increase accordingly, thus resulting in the increase of the total leakage current.
The size of leakage current in a circuit may depend on the input vectors applied to its primary inputs. Further, the leakage current ratio between different input combinations to logic gates of the circuit can be as high as 10. An input vector control method is a technique to reduce the leakage current. For example, during the design of a sequential circuit, which includes multiple stages of flip-flops connected to a combinational logic circuit, minimum leakage bits (MLBs) for reducing leakage current or leakage power consumption for the combinational logic circuit may be calculated during the design stage of the sequential circuit and implemented during the fabrication stage of the sequential circuit. The MLBs then may be applied to the combinational logic circuit during the standby mode of the sequential circuit to reduce the leakage current.
The implementation may be brought about by adding multiplexers to the sequential circuit so that inputs to the flip-flops may be fed to the combinational logic circuit during the active mode of the sequential circuit. Conversely, the MLBs may be fed to the combinational logic circuit using the multiplexers during the standby mode of the sequential circuit. Although the leakage current via the combinational logic circuit may be reduced according to this method, the addition of the multiplexers may eat up a significant real estate of a device using the sequential circuit and/or cause considerable timing overhead. Alternatively, memory may be implemented to the device to store the MLBs so that the MLBs may be available for the combinational logic circuit during the standby mode. Although this method may be more effective in terms of reducing the area overhead than the method employing the multiplexers, the memory may consume considerable power holding and moving the MLBs to the combinational logic circuit.